# Zeljko Zilic - Publications

The list below was kept up-to-date up to 2014; since then, fairly authoritative and easy to check is the data on Google Scholar.

Papers sorted by: Chronological List List by Topics

Publications: Books, Journal Papers, Conferences, Workshops, Patents

### Books

- Y. Fan and Z. Zilic,
*"Accelerating Test, Validation and Debug of High Speed Serial Interfaces"*, Springer, 2011. ISBN: 978-90-481-9397-4 (Publisher Site) - M. Boule and Z. Zilic,
*"Generating Hardware Assertion Checkers: for Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring"*, Springer, 2008. ISBN: 978-1-4020-8585-7 (Publisher Site) - K. Radecka and Z. Zilic,
*"Verification by Error Modeling: Using Testing Techniques for Hardware Verification"*, Kluwer Academic Publishers, 2003. ISBN: 978-1-4020-7652-7 (Publisher Site)

### Book Chapters

- O. Sarbishei, M. Janidarmian, A. R. Fekr, B. Nahill, Z. Zilic and K. Radecka,
*"Multi-sensory Integration Dependability"*, Chapter 18 in Book*Technologies for Smart Sensors and Sensor Fusion*, edited by K. Yallup and K. Iniewski, pp. 319-335, 2013. - B. Mihajlovic, W. Gross and Z. Zilic,
*"Software Debugging Infrastructure for Multi-Core Systems-on-Chip"*, Chapter X in Book*VLSI*, edited by M. Y. Qadri and S. J. Sangwine, 29 pages, 2013. - H. Zarrabi, Z. Zilic, Y. Savaria and A. Al-Khalili,
*"On the Efficient Design and Synthesis of Differential Clock Distribution Networks"*, Chapter 17 in Book*VLSI*, edited by Z-F. Wang, InTech Publishers, ISBN 978-953-307-049-0, 2011, pp. 331-352. - B. Mihajlovic, Z. Zilic and K. Radecka,
*"Infrastructure for Testing Nodes of a Wireless Sensor Network"*, Book Chapter in*Handbook of Research on Developments and Trends in Wireless Sensor Networks: From Principles to Practice*, edited by H. Jin and W-B. Jiang, IGI Global 2010.

### Journal Papers

- A. Roshan Fekr, M. Janidarmian, K. Radecka and Z. Zilic, "A Medical Cloud-Based Platform for Respiration Rate Measurement and Hierarchical Classification of Breath Disorders"
*, Sensors,*, Vol. 14, No. 6, pp. 11204-11224, 2014. - MH. Neishaburi and Z. Zilic, "On a New Mechanism of Trigger Generation for Post-silicon Debugging"
*, IEEE Transactions on Computers,*, Vol. 63, No. 5, pp 1532-1548, 2013. - J. Tong, M. Boule and Z. Zilic, "Test Compaction Techniques for Assertion-Based Test Generation"
*, ACM Transactions on Design Automation of Electronic Systems*, Vol. 19, No. 1, pp. 1-15, (paper 9), Dec. 2013. - MH. Neishaburi and Z. Zilic, "System on Chip Failure Rate Assesment Using the Executable Model of a System"
*, Journal of Computing,*, 2013, pp. 1-15. DOI 10.1007/s00607-013-0372-7. - MH. Neishaburi and Z. Zilic, "A Fault Tolerant Hierarchical Network on Chip Router Architecture"
*, Journal of Electronic Testing and Testing Applications,*, 2013, pp. 1-13. DOI 10.1007/s10836-013-5398-4. - R. Najafi, C. Banville, M. Hafed and Z. Zilic, "Oversampled Multi-Phase Time-Domain Bit-Error Rate Processing for Transmitter Testing"
*, Analog Integrated Circuits and Signal Processing,*, Vol. 77, No. 2, pp. 143-153, Nov. 2013. - MH. Neishaburi and Z. Zilic, "NISHA: A Fault-tolerant NoC Router Enabling Deadlock-free Interconnection of Subsets in Hierarchical Architecture"
*, Journal of Systems Architecture,*, Vol. 59, No. 7, pp. 551-569, Aug. 2013. - MH. Neishaburi and Z. Zilic, "An Infrastructure for Debug Using Clusters of Assertion Checkers"
*, Microelectronics Reliability,*, Vol. 52, No. 11, pp. 2781-2798, November 2012. - O. Sarbishei, K. Radecka and Z. Zilic, "Analytical Optimization of Bit-Widths in Fixed-Point LTI Systems"
*, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,*, Vol. 31, No. 3, pp. 343-355, 2012. - A. Chattopadhyay and Z. Zilic, "Flexible and Reconfigurable Mismatch-tolerant Serial Clock Distribution Networks"
*, IEEE Transactions on Very Large Scale Integrated Circuits*, Vol. 20, No. 3, pp. 523-536, 2012. doi:10.1109/TVLSI.2011.2104982 - Z. Zilic, P. Mishra and S. Shukla "Challenges of Rapidly Emerging Consumer Space Multiprocessors"
*, IEEE Design and Test of Computers*, Vol. 28, No. 3, Jun. 2011, pp. 52-53. - P. Mishra, Z. Zilic and S. Shukla "Guest Editor's Introduction: Multicore SoC Validation with Transaction-Level Models"
*, IEEE Design and Test of Computers*, Vol. 28, No. 3, Jun. 2011, pp. 6-9. - S. Shukla, P. Mishra and Z. Zilic "A Brief History of Multiprocessors and EDA"
*, IEEE Design and Test of Computers*, Vol. 28, No. 3, Jun. 2011, pp. 96. - K. Morin-Allory, M. Boule, D. Borrione and Z. Zilic, "Validating Assertion Language Rewrite Rules and Semantics with Automated Theorem Provers"
*, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 29, No. 9, Sep. 2010, pp. 1436-1448. - S. Bourduas and Z. Zilic, "Modeling and Evaluation of Ring-based Interconnect for Network-on-Chip"
*, Journal of System Architecture*, Vol. 57, No. 1, 2011, pp. 39-60, doi:10.1016/j.sysarc.2010.07.002 - Y. Pang, K. Radecka and Z. Zilic, "Optimization of Imprecise Circuits Represented by Taylor Series and Real-Valued Polynomials"
*, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, Vol. 29, No. 8, August 2010, pp. 1177-1190. - J. Tong, M. Boule and Z. Zilic, "Defining and Providing Coverage for Assertion-Based Dynamic Verification"
*, Journal of Electronic Testing: Theory and Applications*, Vol. 26, Issue 2, April 2010, pp. 211-225. - Y. Fan and Z. Zilic, "Qualifying Serial Interface Jitter Rapidly and Cost-Efficiently"
*, Journal of Electronic Testing: Theory and Applications*, Vol. 26, Issue 2, April 2010, pp. 177-193. - H. Chan and Z. Zilic, "Performance-Driven Circuit and Layout Co-optimization for Deep-Submicron Analog Circuits"
*, Analog Integrated Circuits and Signal Processing*, Vol. 60, No. 1-2, Aug. 2009, pp. 43-55. - S. Bourduas, J-S. Chenard and Z. Zilic, "A Quality Driven Design Approach for Network-on-Chip",
*IEEE Design and Test of Computers (Special Issue on Interconnects for Multicore Chips)*, Vol. 25, No. 5, Oct. 2008, pp. 416-428. - M. Boule and Z. Zilic, "Automata-Based Assertion Checker Synthesis of PSL Properties",
*ACM Transactions on Design Automation of Electronic Systems (Special Issue on High-level Design Validation and Test)*, Vol. 13, No. 1, Paper 4, Jan. - Mar. 2008, 20 pages. - Y. Fan and Z. Zilic, "Bit Error Rate Testing of Communication Interfaces",
*IEEE Transactions on Instrumentation and Measurements*, Vol. 57, No. 5, May 2008, pp. 897-906. - J-S. Chenard, Z. Zilic and M. Prokic "A Laboratory and Teaching Methodology for Wireless and Mobile Embedded Systems",
*IEEE Transactions on Education*, Vol. 51, No. 3, Aug. 2008, pp. 378-384. - M. Boule, J-S. Chenard and Z. Zilic, "Debug Enhancements in Assertion-Checker Generation",
*IET Computers and Digital Techniques (formerly IEE Proceedings on Computers and Digital Techniques), Special Issue on Silicon Debug and Diagnosis,*Vol. 1, No. 6, pp. 669-677, November 2007. - Z. Zilic and K. Radecka, "Scaling and Better Approximating Quantum Fourier Transform by Higher Radices",
*IEEE Transactions on Computers (Special Issue on Nano-Systems and Computing),*Vol. 56, No. 2, pp. 202-207, February 2007. - K. Radecka and Z. Zilic, "Arithmetic Transforms for Compositions of Sequential and Imprecise Datapaths",
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, pp. 1382-1391, July 2006. - A. Chattopadhyay and Z. Zilic, "GALDS: A Complete Framework for Designing Multi-clock ASICs and SoCs",
*IEEE Transactions on Very Large Scale Integration (VLSI*)*Systems*, Vol. 13, No. 6, pp. 641-654, Jun. 2005. - K. Radecka and Z. Zilic, "Design Verification by Test Vectors and Arithmetic Transform Universal Test Sets",
*IEEE Transactions on Computers*, Vol. 53, No. 5, pp. 628-640, May 2004. - S. McCracken, Z. Zilic and H. Chan, "Real Laboratories in Distance Education",
*Journal on Computing and Information Technology"*, Vol. 11, No. 1, pp. 67-76, June 2003. - Z. Zilic and Z. G. Vranesic. "A Deterministic Multivariate Polynomial Interpolation Algorithm for Small Finite Fields",
*IEEE Transactions on Computers*, Vol. 37, No. 2, pp. 1100-1105, September 2002. - M. Boule and Z. Zilic. "An FPGA Move Generator for the Game of Chess",
*Journal of International Computer Chess Association, ICGA Journal*(formerly:*Journal of Computer Chess*) , Vol. 25, No. 2, pp. 85-96, June 2002. - Y. Danan and Z. Zilic. "HANP: A Highly Adaptive Network Processor for FPGAs",
*IEEE Computer Society Technical Committee on Computer Architecture, TCCA, Newsletter, (currently: IEEE Computer Architecture Letters)*No. 10, pp. 64-71, October 2001. - Z. Zilic and Z. G. Vranesic. "Using Decision Diagrams to Design ULMs for FPGAs",
*IEEE Transactions on Computers*, Vol. 47, No. 9, pp. 971-982, September 1998. - Z. Zilic and Z. G. Vranesic. "Polynomial Interpolation Algorithms for Reed-Muller Transform for Incompletely Specified Functions",
*Journal of Multiple-Valued Logic and Soft Computing*. Vol. 2, pp. 217-243, August 1997. - Zeljko Zilic, Synthesis of Parallel Algorithms, by J. H. Reif,
*Journal on Computing and Information Technology*"CIT", Vol. 2, No. 3., pp. 246-248. - Z. Zilic and Z. G. Vranesic. "A Multiple-Valued Reed-Muller Transform for Incompletely Specified Functions",
*IEEE Transactions on Computers*, vol. 44, No. 8, pp. 1012-1020, August 1995. - Z. Zilic, "Experiments with Data Compression Methods in Digital Image Compression",
*Automatika*, vol. 31, No. 1-2, pp. 31-36, June 1990.

### Refereed Conference Papers

- M. Janidarmian, A. Roshan Fekr, K. Radecka and Z. Zilic, "Affordable eRehabilitation Monitoring Platform", Proceedings of IEEE International Humanitarian Technology Conference, IHTC, Jun. 2014.
- A. Roshan Fekr, M. Janidarmian, K. Radecka and Z. Zilic, "Multi-sensor Blind Recalibration in mHealth Applications", Proceedings of IEEE International Humanitarian Technology Conference, IHTC, Jun. 2014.
- J. Tong, M. Boule and Z. Zilic, "Efficient Data Encoding for Improving Fault Simulation Performance in GPUs ", Proceedings of IEEE International Symposium on Electronic System Design, ISED, Dec. 2013.
- M. Janidarmian, A. Roshan Fekr, K. Radecka and Z. Zilic, "Cloud-based Mobile Rehabilitation Platform", Proceedings of Wireless Health, WH2014, Nov. 2013.
- Y. Pang, Q. Lei, J. Lin, Z. Luo, Z. Li, Z. Zilic and K. Radecka, "SAR Computation and Channel Modeling of Body Area Networks", Proceedings of 8th International Conference on Body Area Networks, BODYNETS2013. Sep. 2013.
- A. Ramdial, B. Nahill, H. Zeng, M. Di Natale and Z. Zilic, "A Multicore FPGA Implementation of Wait-free Semantic-Preserving Communication Structures ", Proceedings of 18th International Conference on Emerging Technologies and Factory Automation, EFTA 2013. Sep. 2013.
- J. Tong, M. Boule and Z. Zilic, "Mu-GSIM: A Mutation Testing Simulator on GPUs ", Proceedings of IEEE Asia Symposium on Quality Electronic Design, ASQED, Aug. 2013.
**Best Paper Award** - O. Sarbishei, B. Nahill, A. Roshan Fekr, M. Janidarmian, K. Radecka, Z. Zilic and B. Karajica, "An Efficient Fault-Tolerant Sensor Fusion Algorithm for Accelerometers, Proceedings of 10th Annual Body Sensor Networks Conference, BSN 2013. May 2013.
- A. Suyyagh, B. Nahill, A. Courtemanche, E. Kirshin, Z. Zilic and B. Karajica "Managing the Microprocessor Systems Course Scope Expansion, Proceedings of IEEE International Conference on Microelectronics Systems Education, MSE 2013. Jun. 2013.
- K. Jayawardene, J. Carriot, Z. Zilic and K. Cullen, "Inertial Measurement-based Speed Skater Tracking. ", Proceedings of Wireless Health, WH2012, Oct. 2012.
- A. Roshan Fekr, M. Janidarmian, O. Sarbishei, B. Nahill, K. Radecka and Z. Zilic, "MSE Minimization of Fault-Tolerant Data Fusion with Multi-Sensor Systems. ", Proceedings of IEEE International Conference on Computer Design, ICCD, Oct. 2012.
- E. Kadric, N. Manjikian and Z. Zilic, "An FPGA Implementation for a High-Speed Optical Link with a PCI interface. ", Proceedings of IEEE International Systems on Chip Conference, SOCC, Sep. 2012.
- L. Montesi, Z. Zilic, T. Hanyu and D. Suzuki, "Building Blocks to use in Innovative non-volatile FPGA Architecture Based on MTJs", Proceedings of IEEE International Symposium on VLSI, June 2012.
- R. Najafi, C. Banville, M. Hafed and Z. Zilic, "Oversampled Multi-phase Time-domain Bit-error Rate Processing for Transmitter Testing", Proceedings of IEEE International NEWCAS Conference, June 2012.
- M. Janidarmian, Z. Zilic and K. Radecka, "Issues in Multi-Valued Multi-Modal Sensor Fusion", Proceedings of IEEE International Symposium on Multiple-Valued Logic, ISMVL, June 2012.
- MH. Neishaburi and Z. Zilic, "An Enhanced Debug-aware Network Interface for Network-on-chip", Proceedings of IEEE International Symposium on Quality Electronic Design, ISQED, March 2012.
- Z. Zilic and B. Karajica, "Training for Inter-disciplinary Multi-sensor Design at All Levels", Proceedings of IEEE Interdisciplinary Engineering Design Education Conference, IEDEC'12, Mar. 2012.
- J. Tong, M. Boule and Z. Zilic, "Assertion Clustering for Compacted Test Sequence Generation", Proceedings of IEEE International Symposium on Quality Electronic Design, ISQED, March 2012.
- Z. Zilic and K. Radecka, "Fault Tolerant Glucose Sensor Readout and Recalibration", Proceedings of Wireless Health, WH2011, Oct. 2011.
- MH. Neishaburi and Z. Zilic, "A Fault Tolerant Hierarchical Network on Chip Router", Proceedings of IEEE International Symposium on Defect and Fault Tolerance, DFT 2011, Oct. 2011.
- Z. Zilic and B. Karajica, "High-level Design of Integrated Microsystems - Arithmetic Perspective", Proceedings of IEEE International Symposium on Robotics and Sensor Environments, ROSE 2011, Oct. 2011.
- MH. Neishaburi and Z. Zilic, "Debug-aware AXI-based Network Interface ", Proceedings of IEEE International Symposium on Defect and Fault Tolerance, DFT 2011, Oct. 2011.
- MH. Neishaburi and Z. Zilic, "Hierarchical Embedded Logic Analyzer for Accurate Root-Cause Analysis", Proceedings of IEEE International Symposium on Defect and Fault Tolerance, DFT 2011, Oct. 2011.
- J. Tong, D. Sarraf, M. Boule and Z. Zilic, "Generating Compact Assertions for Control-based Logic Signals", Proceedings of IEEE International Midwest Symposium on Circuits and Systems, MWSCAS2011, August 2011.
- MH. Neishaburi and Z. Zilic, "Failure Rate Assessment Technique Using and Executable Model of the System", Proceedings of Euromicro Conference on Digital System Design, DSD 2011, August 2011.
- Z. Zilic and B. Karajica, "Teaching for Evolution towards Embedded Multi-sensor Interfaces", Proceedings of IEEE International Conference on Microeletronics Systems Education, MSE'11, May 2011.
- MH. Neishaburi and Z. Zilic, "A Distributed AXI-based Platform for Post-Silicon Validation", Proceedings of IEEE International VLSI Test Symposium, VTS 2011, May 2011.
- B. Mihajlovic and Z. Zilic, "Real-Time Address Trace Compression for Emulated and Real System-on-Chip Processor Core Debugging", Proceedings of IEEE International Great Lakes Symposium on VLSI, GLVLSI 2011, May 2011.
- MH. Neishaburi and Z. Zilic, "On Post-Silicon Root-Cause Analysis and Debug using Enhanced Hierarchical Triggers", IEEE European Test Symposium, ETS 2011, May 2011.
- MH. Neishaburi and Z. Zilic, "Post-silicon Infrastructure with Assertion Support", Proceedings of IEEE VLSI Design Automation and Test Conference, VLSI-DAT 2011, Apr. 2011.
- MH. Neishaburi and Z. Zilic, "Enhanced Reliability Aware NoC Router", Proceedings of International Symposium on Quality Electronic Design, ISQED 2011, Mar. 2011.
- Y. Pang, K. Radecka and Z. Zilic, "An Efficient Hybrid Engine to Perform Range Analysis and Allocate Integer Bit-widths for Arithmetic Circuits", Proceedings of Asia and South Pacific Design Automation Conference, ASP-DAC 2011, Jan. 2011.
- O. Abdelfattah, A. Swidan and Z. Zilic, "Direct Residue-to-Analog Conversion Scheme Based on Chinese Remainder Theorem", Proceedings of IEEE International Conference on Electronics, Circuits and Systems, ICECS 2010, Dec. 2010.
- Y. Pang, K. Radecka and Z. Zilic, "An Efficient Method to Perform Range Analysis for DSP Circuits", Proceedings of IEEE International Conference on Electronics, Circuits and Systems, ICECS 2010, Dec. 2010.
- O. Abdelfattah, A. Swidan and Z. Zilic, "Efficient Direct Analog-to-Residue Conversion Schemes", Proceedings of IEEE International Conference on Signals and Electronic Systems, ICSES 2010, Sep. 2010.
- Y. Pang, O. Sarbishei, K. Radecka and Z. Zilic, "Challenges in Verifying and Optimizing Fixed-point Arithmetic-intensive Designs", Proceedings of IEEE International Conference on Automation, Quality and Testing, Robotics, AQTR 2010, May. 2010.
**Invited Talk** - V. Kallankara, MH. Neishabouri, Z. Zilic and K. Radecka, "Using Assertions for Wireless System Monitoring and Debugging ", Proceedings of IEEE International NEWCAS Conference, Jun. 2010.
- MH. Neishabouri and Z. Zilic, "Enabling Efficient Post-silicon Debug by Clustering of Hardware Assertions ", Proceedings of ACM/IEEE Design Automation and Test in Europe, DATE'10, Mar. 2010.
- J. Tong, M. Boule, Z. Zilic, "Airwolf-TG: A Test Generator for Assertion-Based Dynamic Verification ", Proceedings of IEEE High-level Design Validation and Test Workshop, HLDVT'09, Nov. 2009.
- I. Bilicki, V. Sundaresan, D. Maier, N. Grcevski and Z. Zilic, "Cache Line Reservation: Exploring a Scheme for Cache-Friendly Object Allocation", Proceedings of the Center for Advanced Study Conference, CASCON'09, Nov. 2009.
- Y. Fan and Z. Zilic, "A Versatile Scheme for the Validation, Testing and Debugging of High Speed Serial Interfaces", Proceedings of IEEE High-level Design Validation and Test Workshop, HLDVT'09, Nov. 2009.
- A. Chattopadhyay and Z. Zilic, "Serial reconfigurable mismatch-tolerant clock distribution", Proceedings of ACM/IEEE Design Automation Conference, DAC'09, Jul. 2009.
- Z. Zilic, "Designing and Using FPGAs Beyond Classical Binary Logic: Opportunities in Nano-scale Integration Age", Proceedings of IEEE International Symposium on Multiple-Valued Logic, ISMVL'09, May. 2009.
**Invited Talk** - Z. Zilic and K. Radecka, "Enabling Practical Uses of Arithmetic Transform - A Comprehensive Analysis", Proceedings of Ninth International Workshop on Reed-Muller Transform and its Applications, RM'09, May. 2009.
- M. Neishabouri and Z. Zilic, "Reliability Aware NoC Router Architecture Using Input Channel Buffer Sharing", Proceedings of ACM Great Lakes Symposium on VLSI, GLVSI'09, May. 2009.
- Y. Oddos, M. Boule, K. Morin Allory, D. Borrione and Z. Zilic "Automata-Based On-line Test Generator for Assertion-Based Verification", Proceedings of Great Lakes Symposium on VLSI, GLVSI'09, May. 2009.
- Y. Fan and Z. Zilic, "Accelerating Jitter Tolerance Qualification for High Speed Serial Interfaces", Proceedings of International Symposium on Quality Electronic Design, ISQED'09, Mar. 2009.
- K. Morin-Allory, M. Boule, D. Borrione and Z. Zilic, "Proving and Disproving Assertion Rewrite Rules by Automated Theorem Provers", Proceedings of High-level Design Validation and Test Workshop, HLDVT'08, Nov. 2008.
- S. Bourduas, J-S. Chenard and Z. Zilic, "Hyper-Rings: A Cost Effective Improvement of the Hierarchical Rings for Networks-on-Chip",
*Proceedings of IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC'08, Oct. 2008* - M. Boule and Z. Zilic, "Assertion Checkers - Enablers of Quality Design", Proceedings of First Microsystems and Nanoelectronics Research Conference, MNRC'08, Oct. 2008.
- S. Bourduas and Z. Zilic, "A Comparison of Two Multistage Ring Architectures for NoC using High-level Simulation Models", Proceedings of First Microsystems and Nanoelectronics Research Conference, MNRC'08, Oct. 2008.
- Y. Pang, K. Radecka and Z. Zilic, "Fast Algorithms for Compositions of Arithmetic Transforms and their Extensions",
*Proceedings of joint 6th International NEWCAS-TAISA Conference*, Jun. 2008. - Y. Pang, K. Radecka and Z. Zilic, "Verification of Fixed-point Circuits Specified by Taylor Series using Arithmetic Transform",
*Proceedings of joint 6th International NEWCAS-TAISA Conference*, Jun. 2008. - A. Chattopadhyay and Z. Zilic, "Built-in Clock Skew System for On-line Debug and Repair",
*Proceedings of ACM/IEEE Design Automation and Test in Europe, DATE'08, Mar. 2008* - Y. Fan, Y. Cai and Z. Zilic, "A High Accuracy, High Throughput Jitter Test Solution on ATE for 3 Gbps and 6 Gbps Serial-ATA",
*Proceedings of IEEE International Test Conference, ITC'07, Oct. 2007*, 10 pages. - S. Bourduas and Z. Zilic, "Latency Reduction of Global Traffic in Wormwhole-routed Meshes Using Hierarchical Rings for Global Routing",
*Proceedings of 18th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2007*, July 2007, 6 pages - H. Chan and Z. Zilic, "Modeling of Simultaneous Switching Noise-Induced Jitter for System-on-Chip Phase-Locked Loops" ,
*Proceedings of ACM/IEEE Design Automation Conference, DAC07*, June 2007, 6 pages. - Z. Zilic, J-S. Chenard and M. Prokic, "A Laboratory for Wireless and Mobile Embedded Systems",
*Proceedings of IEEE International Conference on Microelectronic Systems Education Conference, MSE07*, June, 2007. - S. Bourduas and Z. Zilic, "A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing",
*Proceedings of ACM/IEEE International Symposium on Networks-on-Chips, NOCS 2007*, Princeton, May 2007. - A. Chattopadhyay and Z. Zilic, "Reconfigurable Clock Distribution Circuitry",
*Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS 2007, May 2007.* - H. Chan and Z. Zilic, "A Performance Driven Layout Compaction Optimization Algorithm for Analog Circuits",
*Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS 2007, May 2007.* - Z. Zilic, K. Radecka and A. Kazampur, "Reversible Circuit Technology Mapping from Non-reversible Specifications",
*Proceedings of ACM/IEEE Design Automation and Test in Europe, DATE 2007*, April 2007. - M. Boule, J-S. Chenard and Z. Zilic, "Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis",
*Proceedings of International Symposium on Quality Electronic Design, ISQED 2007*, March 2007. - M. Boule and Z. Zilic, "Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation",
*Proceedings of the 12th ACM/IEEE Asia and South Pacific Design Automation Conference, ASP-DAC 2007*, January 2007. - H. H. Y. Chan and Z. Zilic, “Parasitic-aware Physical Design Optimization of
Deep Sub-Micron Analog Circuits”,
*Proceedings of IEEE Midwest/NEWCAS Symposium,*pp. 1022-1026, Aug. 2007.**Invited Paper** - A. Chattopadhyay and Z. Zilic, “Design and Operating Characteristics of a

Reconfigurable Clock Distribution Network”,*Proceedings of IEEE Midwest/NEWCAS Symposium*, pp. 9-13, Aug. 2007. - H. Zarrabi, Z. Zilic, A. Al-Khalili and Y. Savaria, “A Methodology for Parallel
Synthesis of Zero Skew Differential Clock Distribution Networks”,
*Proceedings of IEEE Midwest/NEWCAS Symposium*, pp. 799-802, Aug. 2007.

- B. Mihajlovic, Z. Zilic and K. Radecka, “Compression and Encryption of Self-test Programs for Wireless Sensor Network Nodes”,
*Proceedings of IEEE Midwest/NEWCAS Symposium*, pp. 1344-1347, Aug. 2007. - K-L. Lim and Z. Zilic, “An Undersampled Duty Cycle Jitter BIST Circuit”,
*Proceedings of IEEE Midwest/NEWCAS Symposium*, pp. 201-204, Aug. 2007. - S. Bourduas, H. H. Y. Chan and Z. Zilic, “Blocking-Aware Task Assignment for
Wormwhole Routed Network-on-Chip”,
*Proceedings of IEEE Midwest/NEWCAS Symposium*, pp. 1396-1399, Aug. 2007. - Y. Pang, K. Radecka and Z. Zilic, "Algorithms for Compositions of Arithmetic Transforms and Their Extensions",
*Proceedings of IEEE International Conference on Electronics, Circuits and Systems, ICECS06*, Dec. 2006. - Y. Pang, K. Radecka and Z. Zilic, "Arithmetic Transforms of Imprecise Datapaths by Taylor Series Conversion",
*Proceedings of IEEE International Conference on Electronics, Circuits and Systems, ICECS06*, Dec. 2006. - M. Boule and Z. Zilic, Efficient Automata-Based Assertion-Checker Synthesis of PSL Properties ,
*Proceedings of IEEE International High Level Design Validation and Test Workshop, HLDVT 2006*, Nov. 2006. - S. Bourduas, J-S. Chenard and Z. Zilic, "A RTL-Level Analysis of a Hierarchical Ring Interconnect for Network-on-Chip Multi-Processors",
*Proceedings of International System-on-a-Chip Design Conference, ISOCC 2006,*Seoul, Oct. 2006. - Y. Fan, Y. Cai, L. Fang, A. Verma, W. Burchanowski, Z. Zilic and S. Kumar, "An Accelerated Jitter Tolerance Test Technique on ATE for 1.5 Gb/S and 3 GB/s Serial-ATA",
*Proceedings of IEEE International Test Conference, ITC 06*, Oct. 2006. - M. Boule, J-S. Chenard and Z. Zilic, "Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug",
*Proceedings of IEEE International Conference on Computer Design, ICCD 06*, Oct. 2006. - A. Chattopadhyay and Z. Zilic, "Reference-Based Clock Distribution Architectures",
*Proceedings of IEEE International Midwest Symposium on Circuits and Systems*, Aug. 2006. - R. Zhang, Z. Zilic and K. Radecka, "Structuring Measurements for Modeling and the Deployment of Industrial Wireless Networks",
*Proceedings of IEEE International Symposium on Industrial Electronics, ISIE '06*, Jul. 2006. - M. Prokic, J-S. Chenard, R. Zhang and Z. Zilic, "Low-Power Personal Area Network Application Development Platform",
*Proceedings of IEEE International Symposium on Industrial Electronics, ISIE '06,*Jul. 2006. - S. Bourduas, B. Kuo, Z. Zilic and N. Manjikian, "Modeling and Evaluation of an Energy-Efficient Hierarchical Ring Interconnect for System-on-Chip Multiprocessors",
*Proceedings of IEEE-NEWCAS Conference,*Jun. 2006. - A. Chureau, J-F. Boland, Y. Savaria, C. Thibeault and Z. Zilic, "Building Heterogeneous Functional Prototypes Using Articulated Interfaces",
*Proceedings of IEEE-NEWCAS Conference,*Jun. 2006. - R. Zhang, Z. Zilic and K. Radecka, "Energy-Efficient Software-Based Self-Test of Wireless Sensor Network Nodes",
*Proceedings of IEEE VLSI Test Symposium, VTS '06,*Apr. 2006. - M. Boule and Z. Zilic, "Incorporating Efficient Assertion Checkers into Hardware Emulation and Simulation",
*Proceedings of IEEE International Conference on Computer Design, ICCD 05,*Oct. 2005. - M. Prokic, J-S. Chenard, A. U. Khalid, R. Zhang and Z. Zilic, "IEEE 802.15.4 Wireless Conference Management System,
*Proceedings of IEEE International Midwest Symposium on Circuits and Systems,*Aug. 2005. - J-S. Chenard, C. Y. Chiu, Z. Zilic and M. Popovic, "Design Methodology for Wireless Nodes with Printed Antenna",
*Proceedings of ACM/IEEE Design Automation Conference, DAC 05,*Jun. 2005. - J-S. Chenard, A. U. Khalid, M. Prokic, R. Zhang, K-L. Lim, A. Chattopadhyay and Z. Zilic, "Expandable and Robust Laboratory for Microprocessor Systems",
*Proceedings of IEEE International Conference on Microelectronic Systems Education, MSE 05,*Jun. 2005.**Honorary Mention** - H. Chan and Z. Zilic, "Modeling Layout Effects for Sensitivity-based Analog Circuits Optimization",
*Proceedings of International Symposium on Quality Electronic Design, ISQED 05*, Mar. 2005. - J-F. Boland, C. Thibeault and Z. Zilic, "Using Matlab and Simulink in a SystemC Verification Environment",
*Proceedings of Design and Verification Conference, DVCon05*, Feb. 2005.**Best Paper Award** - M. W. Chiang, Z. Zilic, J-S. Chenard and K. Radecka, "Architectures of Increased Availability Wireless Sensor Network Nodes",
*IEEE International Test Conference, ITC*, Oct. 2004. - A. U. Khalid, Z. Zilic and K. Radecka, "FPGA Emulation of Quantum Circuits",
*IEEE International Conference on Computer Design*, Oct. 2004. - J-F. Boland, C. Thibeault and Z. Zilic, "Efficient Multi-Abstraction Level Functional Verification Methodology for DSP Applications",
*Global Signal Processing Expo and Conference, GSPx*, Oct. 2004. - K. L. Lim and Z. Zilic, "A Novel Phase Detector for PAM-4 Clock Recovery in High Speed Serial Links",
*IEEE International System on Chip Conference*Sep. 2004. - Y. Fan and Z. Zilic, "A Novel Scheme of Implementing High Speed AWGN Communication Channel Emulators in FPGAs",
*IEEE International Symposium on Circuits and Systems,*May 2004. - J-F. Boland, A. Chureau, C. Thibeault, Y. Savaria, F. Gagnon and Z. Zilic, "An Efficient Methodology for Design and Verification of an Equalizer for a Software Defined Radio",
*2nd International IEEE Northeastern Workshop on Circuits and Systems, NEWCAS*, May. 2004. - S. McCracken and Z. Zilic, "Design for Testability of FPGA Blocks",
*IEEE International Symposium on Quality Electronic Design,*Mar. 2004. - Y. Fan, Z. Zilic and M-W. Chiang, "A Versatile High Speed Bit Error Rate Testing Scheme",
*IEEE International Symposium on Quality Electronic Design,*Mar. 2004. - H. Chan and Z. Zilic, "Estimating Phase-Locked Loop Jitter due to Substrate Coupling: A Cyclostationary Approach",
*IEEE International Symposium on Quality Electronic Design, ISQED 2004,*Mar. 2004. - M-W. Chiang and Z. Zilic, "Layered Approach to Designing Test System Interfaces,
*Proceedings of IEEE VLSI Test Symposium, VTS2003,*Apr. 2003. - A. Chattopadhyay and Z. Zilic, "A Globally Asynchronous Locally Dynamic System for ASICs and SoCs",
*Proceedings of ACM Great Lakes Symposium on VLSI", GLVLSI,*Apr. 2003. - K. Radecka and Z. Zilic, "On Combinational Verification by Universal Test Set Simulation, SAT and BDDs",
*Proceedings of 6th IEEE International Workshop on Design and Diagnostics of Electronic Circuits and Systems*, Apr. 2003.(reviewed) - Y. Fan and Z. Zilic, "Testing for Bit Error Rates in FPGAs",
*Proceedings of ACM International Symposium on Field Programmable Gate Arrays, FPGA 2003*, Feb. 2003. - K. Radecka and Z. Zilic, "Specifying and Verifying Imprecise Sequential Datapaths by Arithmetic Transforms",
*Digest of Technical Papers, IEEE/ACM International Conference on Computer-Aided Design*, November 2002. - W. Zhu, Z. Zilic and R. Negulescu, "A Single-rail Handshake CDMA Correlator",
*Proceedings of IEEE International Conference on Electronic Circuits and Systems*, Sep. 2002. - A. Chattopadhyay and Z. Zilic, "High Speed Asynchronous Structures for Inter-clock Domain Communication",
*Proceedings of IEEE International Conference on Electronic Circuits and Systems*, Sep. 2002. - C. Cote and Z. Zilic, "Automated SystemC to VHDL Translation in Hardware/Software Codesign",
*Proceedings of IEEE International Conference on Electronic Circuits and Systems*, Sep. 2002. - H. H. Y. Chan and Z. Zilic, "Substrate Coupling Fault Testing in System-on-a-Chip Digital Circuits",
*Proceedings of IEEE International Midwest Symposium on Circuits and Systems*, Tulsa, Aug. 2002.**Invited Talk** - J. Radecki, Z. Zilic and K. Radecka, "Echo Cancellation in IP Networks", invited presentation at
*Proceedings of IEEE International Midwest Symposium on Circuits and Systems*, Tulsa, Aug. 2002. - M. Boule and Z. Zilic, "FPGA Move Generator for the Game of Chess",
*Proceedings of IEEE Custom Integrated Circuits Conference*,*CICC 2002*, May 2002. - Z. Zilic and K. Radecka, "On Role of Super-fast Transforms in Speeding up Quantum Algorithms",
*Proceedings of IEEE International Symposium on Multiple Valued Logic*, May 2002. - B. Polianskikh and Z. Zilic, "Design and Implementation of Error Detection and Correction Circuitry for Multilevel Memory Protection",
*Proceedings of IEEE International Symposium on Multiple Valued Logic*,*ISMVL 2002.*, May 2002. (used in US patent 6,976,194 and 6973613 by Sun Microsystems.) - S. McCracken and Z. Zilic, "FPGA Test Time Reduction Through a Novel Interconnect Testing Scheme",
*Proceedings of ACM International Symposium on Field Programmable Gate Arrays, FPGA 2002.*, February 2002. - K. Radecka and Z. Zilic, "Identifying Redundant Wires for Synthesis and Verification",
*Proceedings of ACM/IEEE Asia and South Pacific Design Automation Conference,ASP-DAC'02*, Bangalore, Jan. 2002. - K. Radecka and Z. Zilic, "Identifying Redundant Gate Replacements in Verification by Error Modeling",
*Proceedings of IEEE International Test Conference*, Oct. 2001. - K. Radecka and Z. Zilic, "Arithmetic Transforms for Verification of Sequential Datapaths",
*Proceedings of IEEE International Conference on Computer Design,*Sept. 2001. - I. Brynjolfson and Z. Zilic, "Clock Managed System on a Chip",
*Proc. IEEE ASIC/SOC Conference*, Sept. 2001. - B. Polianskikh and Z. Zilic, "New Embedded Memory for Enhanced Yield, Performance and Power Consumption",
*Proc. IEEE International Conference on Electronic Circuits and Systems*, Aug. 2001. - H. Chan and Z. Zilic, "A Practical Substrate Modeling Algorithm with Active Guardband Macromodel for Mixed-Signal Substrate Coupling Verification",
*Proc. IEEE International Conference on Electronic Circuits and Systems*, Aug. 2001. - K. Radecka, Z. Zilic and K. Khordoc, "Combinational Verification by Simulation, SAT and BDDs",
*Proc. IEEE International Conference on Electronic Circuits and Systems*, Aug. 2001. - B. Polianskikh and Z. Zilic, "Induced Error-Correcting Code for 2bit-per-cell Multi-Level DRAM",
*Proc. IEEE Midwest Symposium on Circuits and Systems*, Aug. 2001. - H. Chan and Z. Zilic, "Substrate Coupled Noise Reduction and Active Noise Suppression Circuits for Mixed-Signal on a Chip Designs",
*Proc. IEEE International Midwest Symposium on Circuits and Systems*, Aug. 2001.**IEEE Myril B. Reed Best Paper Award** - K. Radecka and Z. Zilic, "Relating Arithmetic and Walsh Spectra for Verification by Error Modeling",
*Proc. 5th International Workshop on Applications of Reed-Muller Expansions in Circuit Design*, Aug. 2001. - Z. Zilic, "Phase- and Delay-Locked Loops Clock Control in Digital Systems",
*On-line Symposium of Electrical Engineering*, Boston, Massachussets, Jul. 2001. (This article has been in**top 10 list of most popular design articles on TechOnline.com for much of 2006**- you can see the link. Also, it is cited in US patent 7,050,034. by Sony Corp.) Slideshow - W. Zhu, R. Negulescu and Z. Zilic, "Using Design Patterns for Fast Hardware/Software Performance Estimation",
*Proc. IEEE International Conference on Telecommunications*, Bucharest, Romania, Jun. 2001. - I. Brynjolfson and Z. Zilic, "A New PLL Design for Clock Management Applications",
*Proc. Int. Symposium on Circuits and Systems*, Sydney, Australia, May 2001. - R. Grindley, T. Abdelrahman, S. Brown, S. Caranci, D. DeVries, B. Gamsa, A. Grbic, M. Gusat, R. Ho, G. Lemieux. K. Loveless, N. Manjikian, P. McHardy, S. Srbljic, M. Stumm Z. Vranesic and Z. Zilic, "The NUMAchine Multiprocessor",
*Proc. Int. Conf. Parallel Processing, ICPP2000*, Toronto, ON, Aug. 2000. - S. McCracken, Z. Zilic and H. Chan, "Real Laboratories in Distance Education",
*Proc. Int. Conf. Adv. Infrastructure for Business, Science and Education on Internet, SSGRR2000*, L'Aquilla, Italy, Aug. 2000. - I. Brynjolfson and Z. Zilic , "Low-Power Clock Management for FPGAs",
*Proc. Custom Integrated Circuits Conference*,*CICC 2000*, Orlando, FL, May. 2000. - K. Radecka and Z. Zilic, "Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling",
*Proc. VLSI Test Symposium, VTS 2000*, Montreal, QC, May 2000. - I. Brynjolfson and Z. Zilic , "FPGA Clock Management for Low-Power Applications",
*Proc. Int. Symposium on FPGAs, FPGA 2000*, Monterrey, CA, Feb. 2000., poster. - Z. Zilic , "Alternatives in Teaching System-Building Skills",
*Proc. Int. Symposium on Microelectronics Systems Education, MSE99*, Arlington, VA, Aug. 1999. - Z. Zilic and K. Radecka, "On Feasible Multivariate Polynomial Interpolations over Arbitrary Fields",
*Proc. ACM International Symposium on Symbolic and Algebraic Computing*, Vancouver, BC, Jul. 1999. - A. Grbic, S. Brown, S. Caranci, R. Grindley, M. Gusat, G. Lemieux, K. Loveless, N. Manjikian, S. Srbljic, M. Stumm, Z. Vranesic, and Z. Zilic, "Design and Implementation of the NUMAchine Multiprocessor,"
*Proc. 35th IEEE Design Automation Conference, DAC98*, San Francisco, Jun. 1998. - Z. Zilic, Z. G. Vranesic and K. Radecka, "A Finite Field Polynomial Interpolation Algorithm",
*Ninth International Approximation Theory Conference, AT IX*, Nashville, Tennessee, Jan. 1998. - Z. Zilic, Z. G. Vranesic and K. Radecka, "A Small Finite Field Polynomial Interpolation Algorithm",
*Fourth International Conference on Finite Fields and Applications, Fq4,*Waterloo, Ontario, Aug. 1997. - S. Brown, N. Manjikian, Z. Vranesic, S. Caranci, A. Grbic, R. Grindley, M. Gusat, K. Loveless, Z. Zilic and S. Srbljic "Experience in Designing a Large-Scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools, in
*Proc. 33rd Design Automation Conference, DAC96*, Las Vegas, Jun. 1996. - Z. Zilic and Z. G. Vranesic, "Parallel Sparse Finite Field Polynomial Interpolation"
*Proc. Workshop on Randomized Parallel Computing,*pp. 21-25, Honolulu, Apr. 1996. - Z. Zilic and Z. G. Vranesic, "New Interpolation Algorithms for Reed-Muller Forms", 26th International Symposium on Multiple-Valued Logic, Santiago De Campostela, Spain, May 1996.
- Z. Zilic and Z. G. Vranesic, Using BDDs to Design ULMs for FPGAs, Proceedings of the Fourth International Symposium on FPGAs, Monterey, February 1996. pp. 24-30. color slides
- Z. Zilic and Z. G. Vranesic, "Reed-Muller Forms for Incompletely Specified Functions via Sparse Polynomial Interpolation", Proceedings of the 25th International Symposium on Multiple-Valued Logic, Bloomington, Indiana, May 1995.
- T. Abdelrahman, S. Brown, T. Mowry, K. Sevcik, M. Stumm, Z. Vranesic, S. Zhou, A. Elkateeb, M. Gusat, P. Pereira, B. Gamsa, R. Grindley, O. Krieger, G. Lemieux, K. Loveless, N. Manjikian, G. Ravindran, S. Srbljic and Z. Zilic , "An Overview of the NUMAchime Multiprocessor Project", Supercomputing Symposium SS'94, pp. 283-295, Toronto, Jun. 1994.
- Z. Zilic and Z. G. Vranesic, "Multiple Valued Logic in FPGAs", Proceedings of 36th Midwest Symposium on Circuits and Systems, pp. 1553-1556, Detroit, Michigan, August 1993.
- Z. Zilic and Z. G. Vranesic, "Current-Mode CMOS Galois Field Circuits", Proceedings of the 23rd International Symposium on Multiple-Valued Logic", pp. 245-250, Sacramento, California, May 1993.
- Z. Zilic and G. Peskir, "Performance Issues in IEEE 802.6 MAN Subnetwork", Proceedings of the Mediterranean IEEE Conference "Melecon '91", pp. 1011-1014, Ljubljana, Slovenia, May 1991.
- V. Glavinic and Z. Zilic, "An Integrated Environment for Specification of OSI Systems", Proceedings of the Mediterranean IEEE Conference "Melecon '91", pp. 1007-1010, Ljubljana, Slovenia, May 1991.
- D. Bosnar and Z. Zilic, "Using Formalisms for Concurrent Process Description in Functional Description of Digital Systems", Conference Etan '91, Ohrid, Macedonia, May 1991.
- Z. Zilic, "Data Compression Methods in Digital Image Compression", Conference YUGRAPH '90, Dubrovnik, Croatia, May 1990.
- Z. Zilic, "Model of One CSMA/CD-Based Access Method", Proceedings of the Conference Etan '90, pp. 243-350, Zagreb, Croatia, May 1990.
**Honorary Mention.**

### Workshop and Conference Papers

- Z. Zilic " Multi-Sensor Integration: From Devices to Applications and Back", 2012 Emerging Technology Conference, CMOS ET, Vancouver, July 2012.
- L. Montesi, Z. Zilic, T. Hanyu and D. Suzuki " Considerations of Incorporating MTJ-based Blocks into Existing FPGA Architecture Families", 20th International Workshop onPost-Binary Ultra Large Scale Integrated Systems, Tuusula, Finland, May 2011.
- J-S. Chenard, M.H. Neishabouri, J. Grabowski, V. Kallankara, B. Mihajlovic and Z. Zilic, " Assertion Checker Instrumentation for Debug in a Distributed Manner", Invited Plenar Presentation at Workshop on Diagnostic Services in Network-on-Chips, Anahiem, June 2010.
- Z. Zilic and K. Radecka, "Enabling Practical Uses of Arithmetic Transforms", Proceedings of Reed-Muller Workshop, RM 2009.
- Z. Zilic, " NoC: Catalyzer or Burden for Validation and Debug of Future Systems?," Invited Panel Presentation at DATE'09 Workshop on Diagnostic Services in Network-on-Chips, Nice, April 2009.
- N. Azuelos, W. Gross and Z. Zilic, " Integrated Functional Solutions for Multi-core Programming, " Proceedings of the Israeli Experimental Systems Conference, SYSTOR, May 2009.
- B. Mihajlovic, M.H. Neishabouri, J. Tong, N. Azuelos, Z. Zilic and W. Gross, " Providing Infrastructure Support to Assist NoC Software Development " Proceedings of Workshop on Diagnostic Services in Networks-on-Chips, DSNOC, Apr. 2009.
- B. Mihajlovic, Z. Zilic and W. Gross, " On Transparently Exploiting Data-level Parallelism on Soft Processors", First Workshop on Soft Processor Systems (WoSPS), Oct. 2008.
- N. Azuelos, W. Gross and Z. Zilic, " SQUID Programming Language for Cell Processor " Cell BE Programming Workshop, May 2008.
- J-S. Chenard and Z. Zilic, " Architecture de Reseau sur Puce pour le Traitement de Donnes Digitales a Tres Haut Debit" FETCH'08, Francophone Doctoral Exposition, Jan. 2008.
- A. Chattopadhyay and Z. Zilic, " A CMOS Averaging Circuit for Programmable Clock Distributions",
*CMC TEXPO Research Exhibition*, Oct. 2007. - J-S. Chenard, M. Boule, S. Bourduas and Z. Zilic, "Hardware Assertion Checkers in On-line Detection of Network-on-Chip Faults",
*Workshop on Diagnostic Services in Networks-on-Chips - Test, Debug and On-line Monitoring*, Nice, April. 2007. - J-F. Boland, C. Thibeault and Z. Zilic, "Sur la Verification des Systemès Mixtes",
*French Doctoral Work Exposition*, 2007. - Z. Zilic, "FPGAs and Modeling Challenge - Quantum Modeling Perspective",
*2nd Workshop on Mixed Molecular/MOS Technology Systems, Advanced Research Development Agency, ARDA*, Park City, Utah, August, 2005,**Invited Talk**. - M. Boule and Z. Zilic, "A Tool for Generating Efficient Emulation Hardware from PSL Assertions,
*Annual CMC TEXPO Exposition, CMC Symposium on Microelectronics Research and Development*, Ottawa, October 2005. - M. Prokic, J-S. Chenard, R. Zhang and Z. Zilic, "Rapid Development and Robust Deployment of Wireless Sensor Network Applications,
*Micronet R&D Annual Workshop,*Aylmer, Apr. 2005. - H. H. Y. Chan and Z. Zilic , ”Automated Radio-frequency Integrated Circuit Software Design Tool using Intelligent Systems,”
*Proceedings of IRIS/PRECARN 14th Annual Canadian Conference on Intelligent Systems*, Ottawa, 2004. - A. Chattopadhyay and Z. Zilic, "Low Power Circuit Techniques for Dynamic Frequency Scaling using Asyncronous Interconnect",
*Micronet R&D Annual Workshop,*Aylmer, Apr. 2004. - M. Boule and Z. Zilic, "From Chess Playing to Theorem Proving: Using Reconfigurable Hardware to Speed up Combinatorial Search,
*Micronet R&D Annual Workshop,*Toronto, Apr. 2003. - Y. Fan and Z. Zilic, "Efficient Implementation of High-speed AWGN Communication Channel Emulators",
*Proceedings of First Northeast Workshop on Circuits and Systems*, Montreal, June 2003. - A. U. Khalid, Z. Zilic and K. Radecka, "Quantum Circuit Emulation by FPGAs and Quantum Measurement by Frames",
*CMC TEXPO Exposition*, 2003. - B. Kuo, K-L. Lim, C-K. Lam and Z. Zilic, "Modeling Networks-on-Chip in StepNP Platform: Study of Ring-of-Rings Topology",
*CMC TEXPO Exposition*, 2003. - A. Chattopadhyay and Z. Zilic, Globally Synchronous, Locally Dinamically Asynchronous Clock Distributions",
*Micronet R&D Annual Workshop,*Toronto, Apr. 2003. - M. Boule and Z. Zilic, "An FPGA Move Generator for the Game of Chess", TEXPO Exposition,
*CMC Symposium on Microelectronics Research and Development*, Ottawa, Jun. 2002. - J-F. Boland, S. Bourduas, Y. Fan, Y. Wang and Z. Zilic, "Intellectual Core Design and Verification",
*TEXPO Exposition, CMC Symposium on Microelectronics Research and Development*, Ottawa, Jun. 2002. - S. McCracken and Z. Zilic, "Using Reconfigurability as a Resource for Speeding up Testing and Diagnosis",
*Micronet R&D Annual Workshop,*Aylmer, Apr. 2002. - K. Radecka and Z. Zilic, "Transformations for Combined Vector/Formal Verification of Datapaths",
*Micronet R&D Annual Workshop*, Aylmer, Apr. 2002. - K. Radecka and Z. Zilic, "Relating Arithmetic and Walsh Spectra in Verification by Implicit Error Modeling",
*Proc. of 5th Intl. Workshop on Applications of the Reed-Muller Expansions in Circuit Design*, pp. 205-214, Aug. 2001. - M. Boule, A. Chattophadyay, M-W. Chiang, S. McCracken and Z. Zilic, MCSoC 2: A Second Generation Managed Clock System-on-a-Chip", TEXPO Exposition, CMC Microelectronics Research and Development, Ottawa, Jun. 2001.
**Honorary Mention** - Y. Danan and Z. Zilic, "HANP: A Highly Adaptive Network Processor for FPGAs", TEXPO Exposition, CMC Microelectronics Research and Development, Ottawa, Jun. 2001.
- K. Radecka, Z. Zilic and K. Khordoc, "Arithmetic Transform in Verification of Sequential Datapaths", Pres.
*Ph. D. Forum at Design Automation Conference*, Jun. 2001. - H. Chan, I. Brynjolfson, Y. Danan, B. Polianskikh and Z. Zilic, "MCSoC: A Research Testbed for Clock Management and Substrate Modeling", Micronet R&D Annual Workshop, Aylmer, Quebec, Apr. 19-20, 2001.
- K. Radecka, Z. Zilic and K. Khordoc, "Verification of Combinational Circuits by Simulations, SAT, ATPG and BDDs", Micronet R&D Annual Workshop, Aylmer, Quebec, Apr. 19-20, 2001.
- I. Brynjolfson and Z. Zilic, "Dynamic Clock Management for Low Power Applications", Micronet R&D Annual Workshop, Ottawa, Ontario, Apr. 19-20, 2000.
- Z. Zilic and K. Radecka, "Don't Care FDD Minimization by Interpolation", International Workshop on Logic Synthesis, IWLS'98, Lake Tahoe, CA., Jun 10-14, 1998.
- Z. Zilic and Z. G. Vranesic, "On feasible transforms for incompletely specified functions", Proceeding of the 1997 Workshop on Post-Binary Ultra-Large Scale Integration, Antinogish, N.S., May 1997.
- Z. Zilic and Z. G. Vranesic, "Application of Order to Interpolation and Learning", Workshop "ORDAL '96", "Order and Decision Making", Ottawa, Aug. 5 - 9, 1996.
- Z. Zilic and Z. G. Vranesic, "Using Decision Diagrams to Design ULMs for FPGAs", Proceeding of the 1996 Workshop on Post-Binary Ultra-Large Scale Integration, Santiago de Campostela, May 1996.
- Z. Zilic, G. Lemieux, K. Loveless, S. Brown and Z. G. Vranesic, "Designing for High Speed-Performance in CPLDs and FPGAs", Proceeding of the Third Canadian Workshop on FPGAs, FPD 95, Montreal, Montreal, June 1995.
- Z. Zilic, On Designing High-Speed Controllers Using FPGAs and PLDs , TRIO/ITRC Retreat, Kingston, Ontario, May 1995.
- Z. Zilic, Multiple-Valued Logic in FPGAs, First University of Toronto "Field-Programmable Retreat", Port Stanton, Ontario, June 1993.
- Z. Zilic and Z. G. Vranesic. "On Retargeting with FPGA Technology", Proceedings of the First Canadian Workshop on Field Programmable Gate Arrays, Winnipeg, May 1993, 14-1 - 14-5.

### Technical Reports

- Z. Zilic, K. Loveless, S. Caranci, R. Grindley, M. Gusat, G. Lemieux and N. Manjikian Implementation of the Processor Card for the NUMAchine Multiprocessor , Technical Report, University of Toronto, Department of Electrical and Computer Engineering, March 1996.
- Z. Vranesic, S. Brown, M. Stumm, S. Caranci, A. Grbic, R. Grindley, M. Gusat, O. Krieger, G. Lemieux, K. Loveless, N. Manjikian, Z. Zilic, T. Abdelrahman, B. Gamsa, P. Pereira, K. Sevcik, A. Elkateeb, S. Srbljic, The NUMAchine Multiprocessor Technical Report, . ( postscript )
- Z. Zilic, "Current-Mode Galois Field Circuits and Implementation of Multiple-Valued Logic Circuits", M. A. Sc. Thesis, University of Toronto, 1993.
- Z. Zilic and M. Molle "Modelling the Exponential Backoff Algorithm in CSMA-CD Networks", Technical Report CSRI-279, Computer Systems Research Institute, Toronto, Oct. 1992.
- Z. G. Vranesic, S. Zaky, C. Hamacher, A. Sanwalka and Z. Zilic: "An Implementation of the Tornet2 Local Area Network", Technical Report, University of Toronto, Department of Electrical Engineering, September 1991.

### Book Reviews

- Zeljko Zilic, Synthesis of Parallel Algorithms, by J. H. Reif, published in
*Journal on Computing and Information Technology*"CIT", Vol. 2, No. 3., pp. 246-248.

### Patents

- Z. Zilic and M. Boule, "Automata Unit, a Tool for Designing Checker Circuitry and a Method of Manufacturing Hardware Circuits Incorporating Checker Circuitry",
*US Patent*, Sep. 2011. 135 pages. (submitted: Sep. 2007) - Z. Zilic, H. Nguyen, G. Powell, W-B. Andrews and R. Stuby, "Signalling Voltage Range Discriminator",
*US Patent 6124732*, Sep. 2000. - L. R. Albu, Z. Zilic, W-B. Leung, R. Stuby, J. Thompson and B. Britton. "A Programmable Clock Manager that Can be Programmed without Reconfiguring the Device",
*US Patent 6060902*, May. 2000. - L. R. Albu, Z. Zilic, W-B. Leung, R. Stuby, J. Thompson and B. Britton. "A Programmable Clock Manager that Can Implement Delay-Locked Loop Function",
*US Patent 604367*7, Mar. 2000. - L. R. Albu, Z. Zilic, W-B. Leung, R. Stuby, J. Thompson and B. Britton. "A Programmable Clock Manager that Can Generate at Least Two Different Clocks",
*US Patent 6028463*, Feb 2000. - I. Brynjolfson and Z. Zilic, Dynamic Clock Divider, US Patent Pending, Jun. 2000.

- Assertion-based Design, Verification, Emulation and Debug
- Circuit and System Testing and Testable Design
- Design Automation and CAD Tools
- Verification: Functional, Arithmetic and System-level
- Clocking and Clock System Design
- Design for Manufacturability and Design Quality
- Systems on Chip, Networks on Chip, Multiprocessors
- Wireless System Design
- Neat Algorithms: Transforms, Interpolations, Reversible, Quantum
- Education Innovations in Computer Engineering

- J-S. Chenard, M. Boule, S. Bourduas and Z. Zilic, "Hardware Assertion Checkers in On-line Detection of Network-on-Chip Faults",
*Workshop on Diagnostic Services in Networks-on-Chips - Test, Debug and On-line Monitoring*, Nice, April. 2007. - M. Boule, J-S. Chenard and Z. Zilic, "Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis",
*Proceedings of International Symposium on Quality Electronic Design, ISQED 2007*, March 2007. - M. Boule and Z. Zilic, "Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation",
*Proceedings of the 12th ACM/IEEE Asia and South Pacific Design Automation Conference, ASP-DAC 2007*, January 2007. - M. Boule and Z. Zilic," Efficient Automata-Based Assertion-Checker Synthesis of PSL Properties,"
*Proceedings of IEEE International High Level Design Validation and Test Workshop, HLDVT 2006*, Nov. 2006. - M. Boule, J-S. Chenard and Z. Zilic, "Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug",
*Proceedings of IEEE International Conference on Computer Design, ICCD 06*, Oct. 2006. - M. Boule and Z. Zilic, "Incorporating Efficient Assertion Checkers into Hardware Emulation and Simulation",
*Proceedings of IEEE International Conference on Computer Design, ICCD 05,*Oct. 2005.

- Y. Fan, Y. Cai, L. Fang, A. Verma, W. Burchanowski, Z. Zilic and S. Kumar, "An Accelerated Jitter Tolerance Test Technique on ATE for 1.5 Gb/S and 3 GB/s Serial-ATA",
*Proceedings of IEEE International Test Conference, ITC 06*, Oct. 2006. - R. Zhang, Z. Zilic and K. Radecka, "Structuring Measurements for Modeling and the Deployment of Industrial Wireless Networks",
*Proceedings of IEEE International Symposium on Industrial Electronics, ISIE '06*, Jul. 2006. - R. Zhang, Z. Zilic and K. Radecka, "Energy-Efficient Software-Based Self-Test of Wireless Sensor Network Nodes",
*Proceedings of IEEE VLSI Test Symposium, VTS '06,*Apr. 2006. - M. W. Chiang, Z. Zilic, J-S. Chenard and K. Radecka, "Architectures of Increased Availability Wireless Sensor Network Nodes",
*IEEE International Test Conference, ITC*, Oct. 2004. - S. McCracken and Z. Zilic, "Design for Testability of FPGA Blocks",
*IEEE International Symposium on Quality Electronic Design,*Mar. 2004. - Y. Fan, Z. Zilic and M-W. Chiang, "A Versatile High Speed Bit Error Rate Testing Scheme",
*IEEE International Symposium on Quality Electronic Design,*Mar. 2004. - M-W. Chiang and Z. Zilic, "Layered Approach to Designing Test System Interfaces,
*Proceedings of IEEE VLSI Test Symposium, VTS2003,*Apr. 2003. - Y. Fan and Z. Zilic, "Testing for Bit Error Rates in FPGAs",
*Proceedings of ACM International Symposium on Field Programmable Gate Arrays, FPGA 2003*, Feb. 2003. (poster) - H. H. Y. Chan and Z. Zilic, "Substrate Coupling Fault Testing in System-on-a-Chip Digital Circuits",
*Proceedings of IEEE International Midwest Symposium on Circuits and Systems*, Tulsa, Aug. 2002.**Invited Talk** - K. Radecka and Z. Zilic, "Identifying Redundant Wires for Synthesis and Verification",
*Proceedings of ACM/IEEE Asia and South Pacific Design Automation Conference,ASP-DAC'02*, Bangalore, Jan. 2002. - K. Radecka and Z. Zilic, "Identifying Redundant Gate Replacements in Verification by Error Modeling",
*Proceedings of IEEE International Test Conference*, Oct. 2001. - K. Radecka and Z. Zilic, "Arithmetic Transforms for Verification of Sequential Datapaths",
*Proceedings of IEEE International Conference on Computer Design,*Sept. 2001. - K. Radecka and Z. Zilic, "Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling",
*Proc. VLSI Test Symposium, VTS 2000*, Montreal, QC, May 2000.

- H. Chan and Z. Zilic, "Modeling of Simultaneous Switching Noise-Induced Jitter for System-on-Chip Phase-Locked Loops" ,
*Proceedings of ACM/IEEE Design Automation Conference, DAC07*, June 2007. - K. Radecka and Z. Zilic, "Arithmetic Transforms for Compositions of Sequential and Imprecise Datapaths",
*IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems*, pp. 1382-1391, July 2006. - Z. Zilic, K. Radecka and A. Kazampur, "Reversible Circuit Technology Mapping from Non-reversible Specifications",
*Proceedings of ACM/IEEE Design Automation and Test in Europe, DATE 2007*, April 2007. - J-S. Chenard, C. Y. Chiu, Z. Zilic and M. Popovic, "Design Methodology for Wireless Nodes with Printed Antenna",
*Proceedings of ACM/IEEE Design Automation Conference, DAC 05,*Jun. 2005. - A. U. Khalid, Z. Zilic and K. Radecka, "FPGA Emulation of Quantum Circuits",
*IEEE International Conference on Computer Design*, Oct. 2004. - K. Radecka and Z. Zilic, "Specifying and Verifying Imprecise Sequential Datapaths by Arithmetic Transforms",
*Digest of Technical Papers, IEEE/ACM International Conference on Computer-Aided Design*, November 2002. - K. Radecka and Z. Zilic, "Identifying Redundant Wires for Synthesis and Verification",
*Proceedings of ACM/IEEE Asia and South Pacific Design Automation Conference,ASP-DAC'02*, Bangalore, Jan. 2002. - Z. Zilic and K. Radecka, "Don't Care FDD Minimization by Interpolation",
*Proceedings of IEEE International Workshop on Logic Synthesis, IWLS'98*, Lake Tahoe, CA., Jun 10-14, 1998. - Z. Zilic and Z. G. Vranesic. "Using Decision Diagrams to Design ULMs for FPGAs",
*IEEE Transactions on Computers*, Vol. 47, No. 9, pp. 971-982, September 1998. - A. Grbic, S. Brown, S. Caranci, R. Grindley, M. Gusat, G. Lemieux, K. Loveless, N. Manjikian, S. Srbljic, M. Stumm, Z. Vranesic, and Z. Zilic, "Design and Implementation of the NUMAchine Multiprocessor,"
*Proc. 35th IEEE/ACM Design Automation Conference, DAC98*, San Francisco, Jun. 1998. - S. Brown, N. Manjikian, Z. Vranesic, S. Caranci, A. Grbic, R. Grindley, M. Gusat, K. Loveless, Z. Zilic and S. Srbljic "Experience in Designing a Large-Scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools, in
*Proc. 33rd IEEE/ACM Design Automation Conference, DAC96*, Las Vegas, Jun. 1996. - Z. Zilic and Z. G. Vranesic. "Polynomial Interpolation Algorithms for Reed-Muller Transform for Incompletely Specified Functions",
*Journal of Multiple-Valued Logic and Soft Computing*. Vol. 2, pp. 217-243, Aug. 1997. - Z. Zilic and Z. G. Vranesic. "A Multiple-Valued Reed-Muller Transform for Incompletely Specified Functions",
*IEEE Transactions on Computers*, vol. 44, No. 8, pp. 1012-1020, August 1995.

- K. Radecka and Z. Zilic,
*"Verification by Error Modeling: Using Testing Techniques for Hardware Verification"*, Kluwer Academic Publishers, 2003, 250 pages. - K. Radecka and Z. Zilic, "Design Verification by Test Vectors and Arithmetic Transform Universal Test Sets",
*IEEE Transactions on Computers*, Vol. 53, No. 5, pp. 628-640, May 2004. - J-F. Boland, C. Thibeault and Z. Zilic, "Using Matlab and Simulink in a SystemC Verification Environment",
*Proceedings of Design and Verification Conference, DVCon05*, Feb. 2005.**Best Paper Award** - A. U. Khalid, Z. Zilic and K. Radecka, "FPGA Emulation of Quantum Circuits",
*IEEE International Conference on Computer Design*, Oct. 2004. - J-F. Boland, C. Thibeault and Z. Zilic, "Efficient Multi-Abstraction Level Functional Verification Methodology for DSP Applications",
*Global Signal Processing Expo and Conference, GSPx*, Oct. 2004. - K. Radecka and Z. Zilic, "Specifying and Verifying Imprecise Sequential Datapaths by Arithmetic Transforms",
*Digest of Technical Papers, IEEE/ACM International Conference on Computer-Aided Design*, November 2002. - K. Radecka and Z. Zilic, "Identifying Redundant Wires for Synthesis and Verification",
*Proceedings of ACM/IEEE Asia and South Pacific Design Automation Conference,ASP-DAC'02*, Bangalore, Jan. 2002. - K. Radecka and Z. Zilic, "Identifying Redundant Gate Replacements in Verification by Error Modeling",
*Proceedings of IEEE International Test Conference*, Oct. 2001. - K. Radecka and Z. Zilic, "Arithmetic Transforms for Verification of Sequential Datapaths",
*Proceedings of IEEE International Conference on Computer Design,*Sept. 2001. - K. Radecka and Z. Zilic, "Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling",
*Proc. VLSI Test Symposium, VTS 2000*, Montreal, QC, May 2000.

- A. Chattopadhyay and Z. Zilic, "Built-in Clock Skew System for On-line Debug and Repair",
*Proceedings of ACM/IEEE Design Automation and Test in Europe, DATE'08, Mar. 2008*. - A. Chattopadhyay and Z. Zilic, "GALDS: A Complete Framework for Designing Multi-clock ASICs and SoCs",
*IEEE Transactions on Very Large Scale Integration (VLSI*)*Systems*, Vol. 13, No. 6, pp. 641-654, Jun. 2005. - A. Chattopadhyay and Z. Zilic, "Reconfigurable Clock Distribution Circuitry",
*Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS 2007, May 2007.* - A. Chattopadhyay and Z. Zilic, "Reference-Based Clock Distribution Architectures",
*Proceedings of IEEE International Midwest Symposium on Circuits and Systems*, Aug. 2006. - K. L. Lim and Z. Zilic, "A Novel Phase Detector for PAM-4 Clock Recovery in High Speed Serial Links",
*IEEE International System on Chip Conference*Sep. 2004. - A. Chattopadhyay and Z. Zilic, "A Globally Asynchronous Locally Dynamic System for ASICs and SoCs",
*Proceedings of ACM Great Lakes Symposium on VLSI", GLVLSI,*Apr. 2003.(acceptance rate: 17%) - A. Chattopadhyay and Z. Zilic, "High Speed Asynchronous Structures for Inter-clock Domain Communication",
*Proceedings of IEEE International Conference on Electronic Circuits and Systems*, Sep. 2002. - I. Brynjolfson and Z. Zilic, "Clock Managed System on a Chip",
*Proc. IEEE ASIC/SOC Conference*, Sept. 2001. - Z. Zilic, "Phase- and Delay-Locked Loops Clock Control in Digital Systems",
*On-line Symposium of Electrical Engineering*, Boston, Massachussets, Jul. 2001. (This article has been in**top 10 list of most popular design articles on TechOnline.com for much of 2006**- you can see the link. Also, it is cited in US patent 7,050,034. by Sony Corp.) Slideshow - I. Brynjolfson and Z. Zilic, "A New PLL Design for Clock Management Applications",
*Proc. Int. Symposium on Circuits and Systems*, Sydney, Australia, May 2001. - L. R. Albu, Z. Zilic, W-B. Leung, R. Stuby, J. Thompson and B. Britton. "A Programmable Clock Manager that Can be Programmed without Reconfiguring the Device",
*US Patent 6060902*, May. 2000. - I. Brynjolfson and Z. Zilic , "Low-Power Clock Management for FPGAs",
*Proc. Custom Integrated Circuits Conference*,*CICC 2000*, Orlando, FL, May. 2000. (cited in US Patent 7072824) - L. R. Albu, Z. Zilic, W-B. Leung, R. Stuby, J. Thompson and B. Britton. "A Programmable Clock Manager that Can Implement Delay-Locked Loop Function",
*US Patent 604367*7, Mar. 2000. - L. R. Albu, Z. Zilic, W-B. Leung, R. Stuby, J. Thompson and B. Britton. "A Programmable Clock Manager that Can Generate at Least Two Different Clocks",
*US Patent 6028463*, Feb 2000. - I. Brynjolfson and Z. Zilic, Dynamic Clock Divider, US Patent Pending, Jun. 2000.

- Y. Fan and Z. Zilic, "Bit Error Rate Testing of Communication Interfaces",
*IEEE Transactions on Instrumentation and Measurements*, Vol. 57, No. 2, Mar. 2008, 10 pages. - Y. Fan, Y. Cai and Z. Zilic, "A High Accuracy, High Throughput Jitter Test Solution on ATE for 3 Gbps and 6 Gbps Serial-ATA",
*Proceedings of IEEE International Test Conference, ITC'07, Oct. 2007*, 10 pages. - A. Chattopadhyay and Z. Zilic, "Built-in Clock Skew System for On-line Debug and Repair",
*Proceedings of ACM/IEEE Design Automation and Test in Europe, DATE'08, Mar. 2008*. - H. Chan and Z. Zilic, "A Performance Driven Layout Compaction Optimization Algorithm for Analog Circuits",
*Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS 2007, May 2007.* - H. Chan and Z. Zilic, "Modeling Layout Effects for Sensitivity-based Analog Circuits Optimization",
*Proceedings of International Symposium on Quality Electronic Design, ISQED 05*, Mar. 2005. - M. W. Chiang, Z. Zilic, J-S. Chenard and K. Radecka, "Architectures of Increased Availability Wireless Sensor Network Nodes",
*IEEE International Test Conference, ITC*, Oct. 2004. - Y. Fan and Z. Zilic, "A Novel Scheme of Implementing High Speed AWGN Communication Channel Emulators in FPGAs",
*IEEE International Symposium on Circuits and Systems,*May 2004. - H. Chan and Z. Zilic, "Estimating Phase-Locked Loop Jitter due to Substrate Coupling: A Cyclostationary Approach",
*IEEE International Symposium on Quality Electronic Design, ISQED 2004,*Mar. 2004. - S. McCracken and Z. Zilic, "Design for Testability of FPGA Blocks",
*IEEE International Symposium on Quality Electronic Design,*Mar. 2004. - Y. Fan, Z. Zilic and M-W. Chiang, "A Versatile High Speed Bit Error Rate Testing Scheme",
*IEEE International Symposium on Quality Electronic Design,*Mar. 2004. - B. Polianskikh and Z. Zilic, "Design and Implementation of Error Detection and Correction Circuitry for Multilevel Memory Protection",
*Proceedings of IEEE International Symposium on Multiple Valued Logic*,*ISMVL 2002.*, May 2002. (used in US patent 6,976,194 and 6973613 by Sun Microsystems.) - H. H. Y. Chan and Z. Zilic, "Substrate Coupling Fault Testing in System-on-a-Chip Digital Circuits",
*Proceedings of IEEE International Midwest Symposium on Circuits and Systems*, Tulsa, Aug. 2002.**Invited Talk** - H. Chan and Z. Zilic, "Substrate Coupled Noise Reduction and Active Noise Suppression Circuits for Mixed-Signal on a Chip Designs",
*Proc. IEEE International Midwest Symposium on Circuits and Systems*, Aug. 2001.**IEEE Myril B. Reed Best Paper Award** - Z. Zilic, H. Nguyen, G. Powell, W-B. Andrews and R. Stuby, "Signalling Voltage Range Discriminator",
*US Patent 6124732*, Sep. 2000.

Systems on Chip, NoCs, Multiprocessors

- S. Bourduas and Z. Zilic, "Latency Reduction of Global Traffic in Wormwhole-routed Meshes Using Hierarchical Rings for Global Routing",
*Proceedings of 18th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2007*, July 2007, 6 pages - S. Bourduas and Z. Zilic, "A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing,
*Proceedings of IEEE International Symposium on Networks-on-Chips, NOCS 2007*, Princeton, May 2007. - S. Bourduas, J-S. Chenard and Z. Zilic, "A RTL-Level Analysis of a Hierarchical Ring Interconnect for Network-on-Chip Multi-Processors",
*Proceedings of International System-on-a-Chip Design Conference, ISOCC 2006,*Seoul, Oct. 2006. - S. Bourduas, B. Kuo, Z. Zilic and N. Manjikian, "Modeling and Evaluation of an Energy-Efficient Hierarchical Ring Interconnect for System-on-Chip Multiprocessors",
*Proceedings of IEEE-NEWCAS Conference,*Jun. 2006. - A. Chureau, J-F. Boland, Y. Savaria, C. Thibeault and Z. Zilic, "Building Heterogeneous Functional Prototypes Using Articulated Interfaces",
*Proceedings of IEEE-NEWCAS Conference,*Jun. 2006. - I. Brynjolfson and Z. Zilic, "Clock Managed System on a Chip",
*Proc. IEEE ASIC/SOC Conference*, Sept. 2001. - R. Grindley, T. Abdelrahman, S. Brown, S. Caranci, D. DeVries, B. Gamsa, A. Grbic, M. Gusat, R. Ho, G. Lemieux. K. Loveless, N. Manjikian, P. McHardy, S. Srbljic, M. Stumm Z. Vranesic and Z. Zilic, "The NUMAchine Multiprocessor",
*Proc. Int. Conf. Parallel Processing, ICPP2000*, Toronto, ON, Aug. 2000. - A. Grbic, S. Brown, S. Caranci, R. Grindley, M. Gusat, G. Lemieux, K. Loveless, N. Manjikian, S. Srbljic, M. Stumm, Z. Vranesic, and Z. Zilic, "Design and Implementation of the NUMAchine Multiprocessor,"
*Proc. 35th IEEE/ACM Design Automation Conference, DAC98*, San Francisco, Jun. 1998. - S. Brown, N. Manjikian, Z. Vranesic, S. Caranci, A. Grbic, R. Grindley, M. Gusat, K. Loveless, Z. Zilic and S. Srbljic "Experience in Designing a Large-Scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools, in
*Proc. 33rd IEEE/ACM Design Automation Conference, DAC96*, Las Vegas, Jun. 1996.

- J-S. Chenard, C. Y. Chiu, Z. Zilic and M. Popovic, "Design Methodology for Wireless Nodes with Printed Antenna",
*Proceedings of ACM/IEEE Design Automation Conference, DAC 05,*Jun. 2005. - M. Prokic, J-S. Chenard, R. Zhang and Z. Zilic, "Low-Power Personal Area Network Application Development Platform",
*Proceedings of IEEE International Symposium on Industrial Electronics, ISIE '06,*Jul. 2006. - R. Zhang, Z. Zilic and K. Radecka, "Structuring Measurements for Modeling and the Deployment of Industrial Wireless Networks",
*Proceedings of IEEE International Symposium on Industrial Electronics, ISIE '06*, Jul. 2006. - R. Zhang, Z. Zilic and K. Radecka, "Energy-Efficient Software-Based Self-Test of Wireless Sensor Network Nodes",
*Proceedings of IEEE VLSI Test Symposium, VTS '06,*Apr. 2006. - M. W. Chiang, Z. Zilic, J-S. Chenard and K. Radecka, "Architectures of Increased Availability Wireless Sensor Network Nodes",
*IEEE International Test Conference, ITC*, Oct. 2004.

Neat Algorithms for Future Microsystems

- Z. Zilic and K. Radecka, "Scaling and Better Approximating Quantum Fourier Transform by Higher Radices",
*IEEE Transactions on Computers (Special Issue on Nano-Systems and Computing),*Vol. 56, No. 2, pp. 202-206, February 2007. - Z. Zilic, K. Radecka and A. Kazampur, "Reversible Circuit Technology Mapping from Non-reversible Specifications",
*Proceedings of ACM/IEEE Design Automation and Test in Europe, DATE 2007*, April 2007. - A. U. Khalid, Z. Zilic and K. Radecka, "FPGA Emulation of Quantum Circuits",
*IEEE International Conference on Computer Design*, Oct. 2004. - Z. Zilic and K. Radecka, "On Role of Super-fast Transforms in Speeding up Quantum Algorithms",
*Proceedings of IEEE International Symposium on Multiple Valued Logic*, May 2002. - K. Radecka and Z. Zilic, "Relating Arithmetic and Walsh Spectra for Verification by Error Modeling",
*Proc. 5th International Workshop on Applications of Reed-Muller Expansions in Circuit Design*, Aug. 2001. - Z. Zilic and Z. G. Vranesic. "A Deterministic Multivariate Polynomial Interpolation Algorithm for Small Finite Fields",
*IEEE Transactions on Computers*,Vol. 37, No. 2, pp. 1100-1105, Sep. 2002. - Z. Zilic and K. Radecka, "On Feasible Multivariate Polynomial Interpolations over Arbitrary Fields",
*Proc. ACM International Symposium on Symbolic and Algebraic Computing*, Vancouver, BC, Jul. 1999. - Z. Zilic and K. Radecka, "Don't Care FDD Minimization by Interpolation",
*Proceedings of IEEE International Workshop on Logic Synthesis, IWLS'98*, Lake Tahoe, CA., Jun 10-14, 1998. - Z. Zilic, Z. G. Vranesic and K. Radecka, "A Finite Field Polynomial Interpolation Algorithm",
*Ninth International Approximation Theory Conference, AT IX*, Nashville, Tennessee, Jan. 1998. - Z. Zilic, Z. G. Vranesic and K. Radecka, "A Small Finite Field Polynomial Interpolation Algorithm",
*Fourth International Conference on Finite Fields and Applications, Fq4,*Waterloo, Ontario, Aug. 1997. - Z. Zilic and Z. G. Vranesic, "On feasible transforms for incompletely specified functions", Proceeding of the 1997 Workshop on Post-Binary Ultra-Large Scale Integration, Antinogish, N.S., May 1997.
- Z. Zilic and Z. G. Vranesic, "Application of Order to Interpolation and Learning",
*Workshop on Partially Ordered Sets and its Applications, "ORDAL '96", "Order and Decision Making*", Ottawa, Aug. 5 - 9, 1996. - Z. Zilic and Z. G. Vranesic, "Parallel Sparse Finite Field Polynomial Interpolation"
*Proc. Workshop on Randomized Parallel Computing,*pp. 21-25, Honolulu, Apr. 1996. - Z. Zilic and Z. G. Vranesic, "New Interpolation Algorithms for Reed-Muller Forms",
*26th International Symposium on Multiple-Valued Logic, Santiago De Campostela*, Spain, May 1996. - Z. Zilic and Z. G. Vranesic, Using BDDs to Design ULMs for FPGAs,
*Proceedings of the Fourth International Symposium on FPGAs*, Monterey, February 1996. pp. 24-30. color slides (cited or used in US Patents: 7167025, 7157933, 7145361, 7126381, 7126373, 7109752)

Computer Engineering Education

- J-S. Chenard, Z. Zilic and M. Prokic, "A Laboratory and Teaching Methodology for Wireless and Mobile Embedded Systems",
*IEEE Transactions on Education*, 2008. - Z. Zilic, J-S. Chenard and M. Prokic, "A Laboratory for Wireless and Mobile Embedded Systems",
*Proceedings of IEEE International Conference on Microelectronic Systems Education, MSE07,*Jun. 2007. - J-S. Chenard, A. U. Khalid, M. Prokic, R. Zhang, K-L. Lim, A. Chattopadhyay and Z. Zilic, "Expandable and Robust Laboratory for Microprocessor Systems",
*Proceedings of IEEE International Conference on Microelectronic Systems Education, MSE05,*Jun. 2005.**Honorary Mention** - S. McCracken, Z. Zilic and H. Chan, "Real Laboratories in Distance Education",
*Journal on Computing and Information Technology"*, Vol. 11, No. 1, pp. 67-76, Jun. 2003. - S. McCracken, Z. Zilic and H. Chan, "Real Laboratories in Distance Education",
*Proc. Int. Conf. Adv. Infrastructure for Business, Science and Education on Internet, SSGRR2000*, L'Aquilla, Italy, Aug. 2000. - Z. Zilic , "Alternatives in Teaching System-Building Skills",
*Proc. Int. Symposium on Microelectronics Systems Education, MSE99*, Arlington, VA, Aug. 1999.